BELT — различия между версиями
Материал из Wiki
ANA (обсуждение | вклад) м |
ANA (обсуждение | вклад) м (→Тестовый план (Edit)) |
||
| Строка 23: | Строка 23: | ||
<html><iframe width='800' height='1200' frameborder='0' src="https://docs.google.com/document/d/1jW88unc9KZ7g8t0NHvQmZ2ne-vGGGCzaWy29ZgoQw_4/pub?embedded=true"></iframe></html> | <html><iframe width='800' height='1200' frameborder='0' src="https://docs.google.com/document/d/1jW88unc9KZ7g8t0NHvQmZ2ne-vGGGCzaWy29ZgoQw_4/pub?embedded=true"></iframe></html> | ||
| + | |||
| + | == TestPlan == | ||
| + | |||
| + | |||
| + | Table 2-7. Recognized (Linkable) Coverage Design Constructs | ||
| + | |||
| + | |||
| + | |||
| + | Table 2-7. Recognized (Linkable) Coverage Design Constructs | ||
| + | |||
| + | <center> | ||
| + | {| cellspacing="0" cellpadding="5" cellspacing="0" cellpadding="5" border="1" | ||
| + | |- | ||
| + | ! Coverage Construct — in “Type” field <br />(case insensitive) | ||
| + | ! Description | ||
| + | ! Syntax <br />(follow the links) | ||
| + | |- | ||
| + | | Assertion | ||
| + | | Assertion statement | ||
| + | | Assertions, Directives, and Generic Coverage Items | ||
| + | |- | ||
| + | | Bin | ||
| + | | Coverage item bin | ||
| + | | Bin Links | ||
| + | |- | ||
| + | | Branch | ||
| + | | Branch coverage scope | ||
| + | | Code Coverage Links | ||
| + | |- | ||
| + | | Condition | ||
| + | | Condition coverage scope | ||
| + | | Code Coverage Links | ||
| + | |- | ||
| + | | CoverGroup | ||
| + | | SystemVerilog covergroup statement | ||
| + | | Covergroups, Coverpoint and Crosses | ||
| + | |- | ||
| + | | CoverPoint | ||
| + | | SystemVerilog coverpoint statement | ||
| + | | Covergroups, Coverpoint and Crosses | ||
| + | |- | ||
| + | | CoverItem | ||
| + | | Generic name for any coverage or design object in a UCDB. This can be used to specify any objects not fitting into another category of construct. | ||
| + | | Assertions, Directives, and Generic Coverage Items | ||
| + | |- | ||
| + | | Cross | ||
| + | | SystemVerilog cross-coverage statement | ||
| + | | Covergroups, Coverpoint and Crosses | ||
| + | |- | ||
| + | | Directive | ||
| + | | PSL cover directives and SystemVerilog "cover" statements/properties | ||
| + | | Assertions, Directives, and Generic Coverage Items | ||
| + | |- | ||
| + | | DU | ||
| + | | All coverage on a given design unit | ||
| + | | Instances and Design Units Links | ||
| + | |- | ||
| + | | Expression | ||
| + | | Expression coverage scope | ||
| + | | Code Coverage Links | ||
| + | |- | ||
| + | | FSM | ||
| + | | State Machine coverage scope | ||
| + | | Code Coverage Links | ||
| + | |- | ||
| + | | Instance | ||
| + | | All coverage on a given instance | ||
| + | | Instances and Design Units Links | ||
| + | |- | ||
| + | | Rule | ||
| + | | Forms a link using an automatically created virtual covergroup “UserRules” — either from a set of pre-defined Rules, or one you create. | ||
| + | | see “” and “” | ||
| + | |- | ||
| + | | Tag | ||
| + | | Forms a link using any coverage tag command arguments which are specified in the Link column. | ||
| + | | _top"” command for syntax | ||
| + | |- | ||
| + | | Test | ||
| + | | Link to test attribute record. This is the test name. | ||
| + | | | ||
| + | |- | ||
| + | | Toggle | ||
| + | | Toggle coverage scope | ||
| + | | | ||
| + | |- | ||
| + | | XML | ||
| + | | Triggers hierarchical (nested) testplan import. See “” | ||
| + | | | ||
| + | |} | ||
| + | </center> | ||
| + | |||
| + | == NEW == | ||
[[Категория:BELT]] | [[Категория:BELT]] | ||
Версия 18:48, 18 ноября 2013
Содержание |
Структура папок проекта
Переменная среды $BELT указывает на размещение проекта на диске
Стурктура папок
$BELT/ /work /sv /vhd /vsim
Запуск моделирования
- Запуск моделирования в Linux (x86-64) из папки $BELT
vsim -64 -do vsim/do_lin.tcl
Описание
Тестовый план (Edit)
TestPlan
Table 2-7. Recognized (Linkable) Coverage Design Constructs
Table 2-7. Recognized (Linkable) Coverage Design Constructs
| Coverage Construct — in “Type” field (case insensitive) |
Description | Syntax (follow the links) |
|---|---|---|
| Assertion | Assertion statement | Assertions, Directives, and Generic Coverage Items |
| Bin | Coverage item bin | Bin Links |
| Branch | Branch coverage scope | Code Coverage Links |
| Condition | Condition coverage scope | Code Coverage Links |
| CoverGroup | SystemVerilog covergroup statement | Covergroups, Coverpoint and Crosses |
| CoverPoint | SystemVerilog coverpoint statement | Covergroups, Coverpoint and Crosses |
| CoverItem | Generic name for any coverage or design object in a UCDB. This can be used to specify any objects not fitting into another category of construct. | Assertions, Directives, and Generic Coverage Items |
| Cross | SystemVerilog cross-coverage statement | Covergroups, Coverpoint and Crosses |
| Directive | PSL cover directives and SystemVerilog "cover" statements/properties | Assertions, Directives, and Generic Coverage Items |
| DU | All coverage on a given design unit | Instances and Design Units Links |
| Expression | Expression coverage scope | Code Coverage Links |
| FSM | State Machine coverage scope | Code Coverage Links |
| Instance | All coverage on a given instance | Instances and Design Units Links |
| Rule | Forms a link using an automatically created virtual covergroup “UserRules” — either from a set of pre-defined Rules, or one you create. | see “” and “” |
| Tag | Forms a link using any coverage tag command arguments which are specified in the Link column. | _top"” command for syntax |
| Test | Link to test attribute record. This is the test name. | |
| Toggle | Toggle coverage scope | |
| XML | Triggers hierarchical (nested) testplan import. See “” |