Спец курс (Избранные главы VHDL)/Вспомним VHDL — различия между версиями

entity example is
generic (
  cnt : integer := 10);
port ( 
  inp   in  : std_logic;
  outp  out : std_logic);
end entity;

architecture beh of trig is
 
begin  -- beh
 
 
 
end beh;

  trig_process: process (clk, rst)
  begin  -- process trig_process
    if rst = '0' then                   -- asynchronous reset (active low)
      data_out <= '0';
    elsif clk'event and clk = '1' then  -- rising clock edge
      data_out <= data_in;
    end if;
  end process trig_process;

data_out_i <= '0' when rst = '0' else
            data_in when clk'event and clk = '1' else
            data_out_i;
data_out <= data_out_i;