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Co-Simulation/Литература — различия между версиями

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м (Содержимое страницы заменено на «{{Co-Simulation TOC}} * [http://www.ftdichip.com/Products/ICs/FT2232H.htm FT2232H - Hi-Speed Dual USB UART/FIFO IC]»)
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* [http://www.ftdichip.com/Products/ICs/FT2232H.htm FT2232H - Hi-Speed Dual USB UART/FIFO IC]
 
* [http://www.ftdichip.com/Products/ICs/FT2232H.htm FT2232H - Hi-Speed Dual USB UART/FIFO IC]
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* [http://microsin.net/adminstuff/hardware/ft2232h-dual-uart-fifo-usb-converter.html полностью переведенный даташит FT2232H - Hi-Speed Dual USB UART/FIFO IC]
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* [http://kit-e.ru/articles/interface/2010_08_90.php http://kit-e.ru/articles/interface/2010_08_90.php]
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==Ссылки==
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* http://www.bluespec.com/products/index.htm Bluespec Core Technology
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** http://csg.csail.mit.edu/6.S078/6_S078_2012_www/resources/bsv_by_example.pdf BSV by Example book
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** https://sites.google.com/a/bluespec.com/learning-bluespec/Home/BSV-Documentation BSV-Documentation
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** http://www.bluespec.com/emulationinfrastructure/emulationinfrastructure.html Emulation Infrastructure
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* http://www.marcopolofpga.co.kr/html/01main_sub01.php?idx=12&PHPSESSID=b096164b3f02ddb0890df0559116f091  MECS ( MarcoPolo co- Emulation System )
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* http://www.xess.com/appnotes/xst3_video.php
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* '''SCE-MI (Standard Co-Emulation Modeling Interface)'''
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** http://www.accellera.org/downloads/standards/sce-mi Download SCE-MI (Standard Co-Emulation Modeling Interface)
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** [http://www.accellera.org/downloads/standards/sce-mi/SCE_MI_v21-110112-final.pdf Standard Co-Emulation Modeling Interface, Release 2.1] (2011-01-21)
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** [https://verificationacademy.com/sessions/sce-mi-20-standard sce-mi-20-standard] (вебинар verificationacademy)
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* '''Готовые решения:'''
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** [http://www.aldec.com/products/HES Aldec's HES™ Hardware Emulation Solutions]
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** alatek
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*** [http://www.design-reuse.com/news/2989/alatek-linux-hardware-accelerator-speeds-hdl-simulators.html Alatek Inc. Announces New LINUX Hardware Accelerator Speeds HDL Simulators]
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*** [http://www.design-reuse.com/news/695/alatek-boosts-performance-mentor-graphics-reg-hdl-simulators-100x.html Alatek Boosts Performance of Mentor Graphics® HDL Simulators By 100x]
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*::: Hardware Embedded Simulation (HES) includes the first year of software maintenance in the purchase price. HES products supporting 2 million FPGA gates start at $125,000. Various hardware configurations are available, and boards that support up to 6 million FPGA gates will be available in 4thQTR of 2001.
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*** [http://hardclub.donntu.edu.ua/rus/etc/hes.htm Hardware Embedded Simulation™ ({{Кр|На русском}})]
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** [http://www.cadence.com/products/sd/rapid_prototyping/pages/resources.aspx Rapid Prototyping Platform] (cadence)
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**[http://www.cadence.com/products/sd/palladium_series/pages/default.aspx '''Cadence Palladium XP''']
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**[http://www.eve-team.com/products/index.php '''EVE Zebu''']
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**[http://www.mentor.com/products/fv/emulation-systems/ '''Mentor Veloce''']
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**[http://www.synopsys.com/Tools/Verification/HardwareAssistedVerification/Pages/default.aspx '''Synopsys Confirma''']
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* http://www.eve-team.com/ - Сейчас часть Synopsys
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* [http://www.dynalith.com/doku.php?id=openidea OpenIDEA]
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** [http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,719,1125&Prod=INREVIUM-7V-2000T  ASIC Development Test Platform with Virtex-7 FPGA By Inrevium™]
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* '''Новости'''
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** [http://www.aldec.com/en/company/news/2012-12-10/140 Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping Platform]
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* Другое
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** [http://masters.donntu.edu.ua/2003/fvti/gez/diss/index.htm Моделирование HDL-проектов на мультипроцессорной системе]
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==== for MES2014 ====
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* [http://www.electronics.ru/journal/article/903 А.Пеженков, Д.Радченко. ''Аппаратные эмуляторы на платформе ZEBU компании EVE'' - Выпуск #4/2005] ([http://www.electronics.ru/files/article_pdf/0/article_903_81.pdf pdf])
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== Accelerating OVM/UVM Testbench Environments in Veloce [http://www.mentor.com/products/fv/emulation-systems/] ==
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[[Файл:Veloce-ovm.png|left]]
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The methodologies defined in the OVM standard, which have now progressed to UVM standards, are supported using the Veloce2 emulation environment. Mentor’s unique TestBench-XPress (TBX) technology delivers the same functionality achievable in simulation, but at 1000s of times faster performance. Additionally, it greatly increases verification productivity by using the same testbench for simulation and Veloce2 accelerated verification.
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<br clear=all />
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== NEW ==

Текущая версия на 13:25, 22 декабря 2013

Co-Simulation
Литература
  • Литература
* PSL * VHDL * OS-VVM *

Содержание

Ссылки


for MES2014

Accelerating OVM/UVM Testbench Environments in Veloce [1]

Veloce-ovm.png

The methodologies defined in the OVM standard, which have now progressed to UVM standards, are supported using the Veloce2 emulation environment. Mentor’s unique TestBench-XPress (TBX) technology delivers the same functionality achievable in simulation, but at 1000s of times faster performance. Additionally, it greatly increases verification productivity by using the same testbench for simulation and Veloce2 accelerated verification.


NEW

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