ПЦУСБ/Лабораторная работа 2 — различия между версиями

library ieee;
use ieee.std_logic_1164.all;
 
entity NO2 is
 
  port (
    A, B : in  std_logic;
    Y    : out std_logic);
 
end entity NO2;
 
architecture beh of NO2 is
 
begin  -- architecture beh
 
  Y <= not (A or B) after 3 ns;
 
end architecture beh;

library ieee;
use ieee.std_logic_1164.all;
 
entity NA3 is
 
  generic (
    del : time := 4 ns);
 
  port (
    A : in  std_logic;
    B : in  std_logic;
    C : in  std_logic;
    Y : out std_logic);
 
end entity NA3;
 
architecture beh of NA3 is
 
begin  -- architecture beh
 
  Y <= not (A and B and C) after del;
 
end architecture beh;

library ieee;
use ieee.std_logic_1164.all;
 
entity NAO22 is
 
  generic (
    del : time := 5 ns);
 
  port (
    A : in  std_logic;
    B : in  std_logic;
    C : in  std_logic;
    D : in  std_logic;
    Y : out std_logic);
 
end entity NAO22;
 
architecture beh of NAO22 is
 
begin
 
  Y <= not ((A or B) and (C or D)) after del;
 
end architecture beh;

library ieee;
use ieee.std_logic_1164.all;
 
entity NOAO2 is
 
  generic (
--    del : time := 570 ps);
    del : time := 5 ns);
 
  port (
    A : in  std_logic;
    B : in  std_logic;
    C : in  std_logic;
    D : in  std_logic;
    Y : out std_logic);
 
end entity NOAO2;
 
architecture beh of NOAO2 is
 
begin
 
  Y <= not (A or (B and (C or D))) after del;
 
end architecture beh;

-------------------------------------------------------------------------------
-- Project    : Lab02
-- Variant    : 01
-- Author     : ANA (XXX group)
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
package lib is
 
  component n is
    generic (
      del : time := 2 ns);
    port (
      A : in  std_logic;
      Y : out std_logic);
  end component n;
 
  component NO2 is
    port (
      A, B : in  std_logic;
      Y    : out std_logic);
  end component NO2;
 
  component NA3 is
--  generic (
--      del : time :);
    port (
      A : in  std_logic;
      B : in  std_logic;
      C : in  std_logic;
      Y : out std_logic);
  end component NA3;
 
  component NAO22 is
    generic (
      del : time := 5 ns);
    port (
      A : in  std_logic;
      B : in  std_logic;
      C : in  std_logic;
      D : in  std_logic;
      Y : out std_logic);
  end component NAO22;
 
  component NOAO2 is
    generic (
      del : time := 5 ns);
    port (
      A : in  std_logic;
      B : in  std_logic;
      C : in  std_logic;
      D : in  std_logic;
      Y : out std_logic);
  end component NOAO2;
 
end package lib;

-------------------------------------------------------------------------------
-- Project    : Lab02
-- Variant    : 01
-- Author     : ANA (XXX group)
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
 
entity sch01 is
 
  port (
    X : in  std_logic_vector(3 downto 1);
    Y : out std_logic_vector(2 downto 1));
 
end entity sch01;
 
architecture sch of sch01 is
 
  signal x1_n, x2_n, x3_n : std_logic;
  signal DD3_Y  : std_logic;
  signal DD4_Y  : std_logic;
  signal DD5_Y  : std_logic;
  signal DD5_YN : std_logic;
  signal DD8_Y  : std_logic;
 
begin
 
  DD1: n port map (X(1), X1_N);
  DD2: n port map (A => X(2), Y => X2_N);
   DD3: NO2
    port map (
      A => X1_N,
      B => X(2),
      Y => DD3_Y);
  DD4: NO2
    port map (X(1), X(3), DD4_Y);
 
  DD5: NA3
    port map (
      A => x2_N,
      B => X(1),
      C => x(3),
      Y => DD5_Y);
  DD6: n port map (DD5_Y, DD5_YN);
  DD7: n port map (X(3), X3_N);
  DD8: NA3
    port map (
      A => x(1),
      B => DD4_Y,
      C => x(3),
      Y => DD8_Y);
 
  DD9: NAO22
    port map (
      A => DD3_Y,
      B => DD4_Y,
      C => DD8_Y,
      D => DD5_YN,
      Y => Y(1));
 
  DD10: NOAO2
    port map (
      A => X(1),
      B => X3_N,
      C => DD3_Y,
      D => DD5_Y,
      Y => Y(2));
 
end architecture sch;

-------------------------------------------------------------------------------
-- Project    : Lab02
-- Variant    : 01
-- Author     : ANA (XXX group)
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity sch01_tb is
end entity sch01_tb;
 
architecture tb of sch01_tb is
 
  -- components
  component sch01 is
    port (
      X : in  std_logic_vector(3 downto 1);
      Y : out std_logic_vector(2 downto 1));
  end component sch01;
 
  component sch01a is
    port (
      X : in  std_logic_vector(3 downto 1);
      Y : out std_logic_vector(2 downto 1));
  end component sch01a;
 
  signal X : std_logic_vector(2 downto 0) := (others => '0');
  signal Y1 : std_logic_vector(2 downto 1);
  signal Y2 : std_logic_vector(2 downto 1);
 
  signal OK : std_logic;
 
begin
 
  DUT1: sch01
    port map (
      X => X,
      Y => Y1);
 
  DUT2: sch01a
    port map (
      X => X,
      Y => Y2);
 
  x(0) <= not x(0) after 50 ns;
  x(1) <= not x(1) after 100 ns;
  x(2) <= not x(2) after 200 ns;
 
  OK <=
    '1' when Y1 = Y2 else
    'X';
 
end architecture tb;

library ieee;
use ieee.std_logic_1164.all;
-- пакеты для ввода/вывода
use std.textio.all;
use ieee.std_logic_textio.all;
 
-------------------------------------------------------------------------------
 
--entity sch01_tb is
--end entity sch01_tb;
 
-------------------------------------------------------------------------------
 
architecture tb2 of sch01_tb is
 
  component sch01 is
    port (
      X : in  std_logic_vector(3 downto 1);
      Y : out std_logic_vector(2 downto 1));
  end component sch01;
 
  component sch01a is
    port (
      X : in  std_logic_vector(3 downto 1);
      Y : out std_logic_vector(2 downto 1));
  end component sch01a;
 
  signal X  : std_logic_vector(2 downto 0) := (others => '0');
  signal Y1 : std_logic_vector(2 downto 1);
  signal Y2 : std_logic_vector(2 downto 1);
 
  signal OK     : std_logic;
  signal All_Ok : std_logic;
  signal strob  : std_logic := '0';
 
  signal clock_time             : time := 0 ns;
  signal delay_y1, delay_y1_max : time := 0 ns;
  signal delay_y2, delay_y2_max : time := 0 ns;
 
begin
 
  DUT1 : sch01
    port map (
      X => X,
      Y => Y1);
 
  DUT2 : sch01a
    port map (
      X => X,
      Y => Y2);
 
-- формирование входных воздействий
  x(0) <= not x(0) after 50 ns;
  x(1) <= not x(1) after 100 ns;
  x(2) <= not x(2) after 200 ns;
 
-- процесс формирует стробирующий сигнал,
-- по положительному фронту которого происходит сравнение
-- выходов двух моделей и вывод в транскрипт значений задержки
  process is
  begin  -- process
    strob <= '0';
    wait for 45 ns;
    strob <= '1';
    wait for 5 ns;
  end process;
 
-- проверка соответствия ответов
  OK <=
    '1' when Y1 = Y2 else
    'X';
 
-- определение времени смены входных сигналов
  clock_time <=
    now when x(0)'event else
    clock_time;
 
-- определение задержки распространения сигнала от входов к выходам
  delay_y1 <=
    now - clock_time when y1(1)'event else
    0 ns             when x(0)'event else
    delay_y1;
 
  delay_y2 <=
    now - clock_time when y1(2)'event else
    0 ns             when clock_time'event else
    delay_y2;
 
-- определение максимальной задержки распространения сигнала
  delay_y1_max <=
    delay_y1 when delay_y1 >= delay_y1_max else
    delay_y1_max;
 
  delay_y2_max <=
    0 ns     when now < 100 ns else
    delay_y2 when delay_y2 >= delay_y2_max else
    delay_y2_max;
 
-- процесс для вывода значений задержки в транскрипт
  process (strob)
  begin  -- process
    if strob'event and strob = '1' then
--      write(OUTPUT, " " & time'image(now) & " " & to_string(x) & " " & to_string(y1) & " " & time'image(delay_y2)& " " & time'image(delay_y1) & LF );
 
      write(OUTPUT, " " & to_string(x) & " " & to_string(y1) & " " & time'image(delay_y2)& " " & time'image(delay_y1) );
      if y1 = y2 then
        All_Ok <= '1';
        write(OUTPUT, " Ok" & LF);
      else
        All_Ok <= 'X';
        write(OUTPUT, " FAIL" & LF);
      end if;
 
    end if;
 
  end process;
 
end architecture tb2;