VHDL-2019 — различия между версиями

Версия 22:44, 27 апреля 2021

Webinar: New Features in VHDL 2019 - WEBINAR (требуется регистрация для просмотра)
http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/VHDL2017 - Описание изменений языка VHDL-2019
https://vhdlwhiz.com/vhdl-2019/ - описание нововведений в VHDL-2019
https://standards.ieee.org/standard/1076-2019.html Ссылка на стандарт языка VHDL-2019
VHDL-2019: the Users Standard - Краткое описание нововведений VHDL-2019 на сайте osvvm.org
VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment
What's new in VHDL 2019?, часть 2, Часть 3, Часть 4- Описание нововведений VHDL-2019 от создателей текстового редактора Sigasi
VHDL-2019 example of conversion from integer to std_logic_vector -> edaplayground Example: VHDL-2019 handle of receiver of return value

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 * [https://osvvm.org/archives/1806 VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and The New Environment]
 * [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part1/#:~:text=VHDL%202019%20improves%20many%20aspects,and%20clarity%20of%20the%20code. What's new in VHDL 2019?], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part2/ часть 2], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part3/ Часть 3], [https://insights.sigasi.com/tech/what-is-new-in-vhdl-2019-part4/ Часть 4]- Описание нововведений VHDL-2019  от создателей текстового редактора Sigasi
+* [https://electronics.stackexchange.com/questions/4482/vhdl-converting-from-an-integer-type-to-a-std-logic-vector VHDL-2019 example of conversion from integer to std_logic_vector] -> [https://www.edaplayground.com/x/qJLb edaplayground Example: VHDL-2019 handle of receiver of return value]
 * https://opensource.ieee.org/vasg/Packages - исходные коды IEEE-пакетов VHDL