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Co-Simulation/Техническое задание

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Co-Simulation

Литература

* PSL * VHDL * OS-VVM *

4.4.4 Controlled and uncontrolled time

Co-Simulation(SCE-MI)-Fig-4.5-cclock-and-uclock.png

Any transactor can instruct the SCE-MI infrastructure to stop the controlled clock and thus cause controlled time to freeze.

  • All transactors are told by the SCE-MI infrastructure when the controlled clock is stopped.
  • Any transactor shall function correctly if controlled time is stopped due to operations of another transactor, even if the transactor in question does not itself need to stop the clock.
  • A transactor might need to stop the controlled clock when performing operations that involve decomposition or composition of transactions arriving from or going to a message channel.
  • The DUT is always clocked by one or more controlled clocks which are controlled by one or more transactors.
  • A transactor shall sample DUT outputs on valid controlled clock edges. The transactor can use a clock control macro to know when edges occur.
  • All transactors are clocked by a free running uncontrolled clock provided by the SCE-MI hardware side infrastructure.

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