SystemC Tutorial for VHDL Engineers

• Источник
• Ports and Data Types

Part 1

Revision 0.0

Last Updated: 18 August 2007

On the next few web pages you will find a brief tutorial on the powerful SystemC programming language. The tutorial is mainly targeted at the VHDL engineer but Verilog users should have no problem understanding the comparative VHDL examples and language constructs given. No C++ knowledge is required, however, it is advisable to study some C and C++ constructs and methodologies during the tutorial.

This tutorial discusses SystemC at the so called RTL level, that is, it discusses language constructs at the same level as synthesizable VHDL/Verilog. This might not be the best usage of the language and one might argue that SystemC should be used for high-level modeling and not for RTL coding. Although I agree with this statement to a certain degree, I believe that you can learn a new language much quicker if you can draw similarities with a language you already know which in this tutorial's case is VHDL. Once you understand the basic language constructs you can more easily move into all the wonderful high-level techniques like Constraint Random(CR) testing and Transaction Level Modeling (TLM).

I should point out that this tutorial is not written to convince the reader to swap his VHDL/Verilog language for SystemC. On the contrary, VHDL and Verilog have build up quite a powerful arsenal of EDA tools, IP cores, know-how and user base something which is not be easily overtaken by a new language. However, in the field of high-level modeling and complex testbench development there is a vacancy. This vacancy has been filled for Verilog users with SystemVerilog but for VHDL the job interview is still on-going :-).

SystemC should be considered as a powerful add-on to any engineer's EDA language toolkit!

Writing a tutorial can be tricky especially when the writer (me) doesn't have years of experience writing SystemC code. So if you find anything wrong or have some tips and tricks please let me know, you can send me comments anonymously if you prefer.

Table of Contents

• 1 Introduction
  • 1.1 Free VCD Viewers
  • 1.2 SystemC "Hello World"
  • 1.3 Simulate
  • 1.4 HelloWorld 2
• 2 Ports and Data Types
  • 2.1 SystemC I/O Ports
  • 2.2 SystemC Data Types
• 3 Processes
  • 3.1 Example FF using SC_METHOD and SC_THREAD
  • 3.2 Sensitivity List
  • 3.3 Process Synchronization and Deltas
  • 3.4 Process Variables
  • 3.5 SC_HAS_PROCESS
• 4 Hierarchy
  • 4.1 SC_MAIN
  • 4.2 Simple Example
  • 5 Debugging
  • 5.1 Using VCD files
  • 5.2 Using textio
  • 5.3 Using Assertions
  • 5.4 Using a Debugger
• Appendix A