Questa SIM User's Manual/GUI Elements of the Assertions Window

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GUI Elements of the Assertions Window

This section describes GUI elements specific to this Window.

Column Descriptions

Table 4-2. Assertions Window Columns

Column Title	Description
Active Count	The number of active assertion attempts at the current time. Only enabled if the simulator is invoked with the “-assertdebug” option or the .ini file variable AutoExclusionsDisable is set to 1.
Assertion Expression	Displays the actual assertion expression.
Assertion Type	Indicates the assertion type: Immediate or Concurrent.
Attempt Count	The number of times the assertion has been attempted. This is the number of assertion clocks for clocked assertions, or the number of passes and fails for unclocked assertions. This column is populated when you specify “-assertcover” or “-assertdebug” for vsim, or if either the target="_top" or target="_top" .ini file variable is set to 1.
ATV	Indicates the status of assertion thread viewing: on or off. Only enabled if the simulator is invoked with the "-assertdebug" option or the .ini file variable AssertionDebug is set to 1.
Cumulative Threads	The cumulative thread count for the assertion. This count is designed to highlight those directives that are starting too many attempts. For example, given the assertion: assert property ((@posedge clk) a |=> b); If ‘a’ is true throughout the simulation, then the above assertion will start a brand new attempt at every clock. An attempt, once started, will only be alive until the next clock. So this assertion will not appear abnormally high in the Memory and Peak Memory columns, but it will have a high count in the Cumulative Threads column.
Design Unit	Identifies the design unit to which the assertion is bound.
Design Unit Type	Identifies the HDL type of the design unit.
Disable Count	The number of assertion attempts that have been disabled due to either an abort expression becoming true (PSL) or a disable if expression becoming true (SVA). This column is populated when you specify “-assertcover” or “-assertdebug” for vsim, or if either the target="_top" or target="_top" .ini file variable is set to 1.
Enable	Identifies whether failure checking is active for the assertion.
EOS Note	Identifies when assertion directives are active at the end of simulation (EOS): on or off. Refer to the target="_top" command. If the assert directive is strong, the EOS Note column will report both the "active at end of simulation" note along with a strong error message.
Failure Count	Total number of times the assertion has failed in the current simulation.
Failure Limit	The number of times the simulator will respond to a failure event on an assertion.
Failure Log	enabled — failure messages will be logged to the transcript. disabled — failure messages will not be logged to the transcript.
Formal	Indicates formal analysis has been performed. Data appears in this column only during post-process analysis (Coverage View mode). Displayed values include: blank — no formal analysis has been performed assumption — indicates that property was used as an assumption in the formal analysis conflict — indicates conflict when inconsistent data merged in formal analysis failure — indicates formal analysis has determined that property can fail inconclusive — indicates formal analysis has not proved or falsified the property. See Proof Radius column for amount of formal analysis performed. proof — indicates formal analysis has proven that property cannot fail for all legal stimulus vacuous — indicates formal analysis has proven that the antecedent of the property cannot be reached; property needs to be examined closer
FPSA Actions	Displays a matrix of information relating the current action for each possible state: Failure, Pass, Start, and Antecedent. The field will always show four letters that indicate the current action: C - Continue B - Break E - Exit S - Subroutine Call where the order of the letters relates to the state: F - Failure P - Pass S - Start A - Antecedent For example, if you see CCSB, you can derive the following: Failure state - Continue action Pass state - Continue action Start state - Subroutine Call action Antecedent state - Break action
Included	Indicates whether the Assertion is included in (check mark) or excluded from (X mark) aggregate statistics and reports.
Language	Identifies the HDL used to write the assertion.
Memory	Tracks the current memory used by the assertion.
Name	Identifies the assert directive you specified in the assertion code.
Pass Count	The total number of times the assertions has passed in the current simulation. This column is populated when you specify “-assertcover” or “-assertdebug” for vsim, or if either the target="_top" or target="_top" .ini file variable is set to 1.
Pass Log	enabled — pass messages will be logged to the transcript. disabled — pass messages will not be logged to the transcript. Only enabled if the simulator is invoked with the "-assertdebug" option or the .ini file variable AssertionDebug is set to 1.
Peak Active Count	The peak simultaneously active thread count that has occurred up to the current time. Peak Active Count will also be shown in reports created with the target="_top" command. Only enabled if the simulator is invoked with the "-assertdebug" option or the .ini file variable AssertionDebug is set to 1.
Peak Memory	The peak memory used by the assertion.
Peak Memory Time	Indicates the simulation run time at which the peak memory usage occurred.
Proof Radius	Indicates that the property has been verified to a depth of x number of cycles in the formal analysis. Shown as positive integer. Data appears in this column only during post-process analysis (Coverage View mode).
Vacuous Count	The number of assertion attempts that have succeeded vacuously, that is, if the left hand side of an implication is false on a clock edge. This column is populated when you specify “-assertcover” or “-assertdebug” for vsim, or if either the target="_top" or target="_top" .ini file variable is set to 1.

Popup Menu

Right-click in the window to display the popup menu and select one of the following options:

Table 4-3. Assertions Window Popup Menu

Popup Menu Item	Description
Add	Add information about the selected assertions to the specified window.
View Source	Opens a source file for the selected assertion.
Enable ATV	Enables an assertion for use with the ATV Window.
View ATV	Opens an ATV window for the selected assertion.
Report	Generates a report about the selected assertion.
Configure	Allows you to configure the simulators behavior for the selected assertion.
Enable	Enables checking of the assertion for failures during the simulation
Failure Log	Logs failure messages (PSL only) to the transcript.
Pass Log	Logs pass messages (PSL only) to the transcript. Only enabled if the simulator is invoked with the "-assertdebug" option or the .ini file variable AssertionDebug is set to 1.
... Action	Allows you to take specified actions when the selected assertions meet certain conditions.
Test Analysis	When a UCDB file is selected, allows you to Find Tests with: Least Coverage, Most Coverage, Zero Coverage, or Non-Zero Coverage; Rank Most Effective Tests; produce a Summary report.
XML Import Hint	Displays the XML Import Hint dialog box with information about the Link Type and Name.
Filter	Setup — Opens Filter Setup dialog Apply — Applies filter to selected item(s)
Expand	Expand or collapse the hierarchy.
Display Options	Allows you to control the appearance of information in the window.
Exclude Selected	Excludes selected item(s) from coverage statistics collection and reports
Clear Exclusion	Clears coverage exclusion for selected item(s)