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| − | == Analyzing Assertions and Cover Directives ==
| + | * [[/Analyzing Assertions and Cover Directives|Analyzing Assertions and Cover Directives]] |
| | + | * [[/GUI Elements of the Assertions Window|GUI Elements of the Assertions Window]] |
| | | | |
| − | The following tasks can be used for analyzing assertions and cover directives:
| + | [[Категория:vsim]] |
| − | | + | |
| − | * Viewing Assertions in the Assertions Window
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| − | * Viewing Cover Directives in the Cover Directives Window
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| − | * Viewing Memory Profile Data
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| − | * Viewing Assertions and Cover Directives in the Wave Window
| + | |
| − | * Comparing Assertions
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| − | | + | |
| − | === Viewing Assertions in the Assertions Window ===
| + | |
| − | | + | |
| − | <!--
| + | |
| − | The Assertions windows displays simulation data about assertions. To open the Assertions window, select View > Coverage > Assertions from the menus.-->
| + | |
| − | Окна Утверждения (Assertions windows) отображают данные моделирования об утверждениях. Чтобы открыть окно Утверждения, выберите ''View → Coverage → Assertions'' из меню.
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| − | | + | |
| − | <!-- Figure 21-17 shows SystemVerilog assertions in the Assertions window. SV assertions are indicated by a light blue triangle. PSL assertions (not shown) are indicated by a purple triangle.-->
| + | |
| − | Рисунок 21-17 показывает SystemVerilog утверждения в окне Утверждения. Утверждения SV обозначены голубым треугольником. PSL утверждений (не показаны) обозначаются фиолетовым треугольником.
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| − | | + | |
| − | {| align=center
| + | |
| − | ! [[Файл:Vsim Assertions window.gif]]
| + | |
| − | |-
| + | |
| − | ! Figure 21-17. SystemVerilog Assertions in the Assertions Window
| + | |
| − | |}
| + | |
| − | | + | |
| − | <!--
| + | |
| − | The Assertions window lists all embedded and external assert directives that were successfully compiled and simulated during the current session. The plus sign (’+’) to the left of the Name field lets you expand the assertion hierarchy to show its elements (properties, sequences, clocks, and HDL signals).
| + | |
| − | -->
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| − | В окне Утверждения перечислены все встроенные и внешние директивы утверждений, которые были успешно скомпилированы и моделируемые в ходе текущей сессии. Знак плюс ('+') слева от поля "Name" позволяет расширить (раскрыть) иерархию утверждения, чтобы показать её элементы (свойства, последовательности, синхронизацию и HDL сигналы).
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| − | | + | |
| − | <!-- The Assertions window includes several columns for displaying information about assertions. See GUI Elements of the Assertions Window for a description of each field.-->
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| − | Окно Утверждения включает в себя несколько столбцов для отображения информации о утверждениях. Смотри [[GUI Elements of the Assertions Window]] для описания каждого поля.
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| − | <!-- When assertions fire with failure messages, the Assertions window displays the name and failure count in red, both during simulation and in post-simulation mode (Figure 21-18).
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| − | -->
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| − | Когда утверждения выдают сообщений об ошибке, окно Утверждения отображает имя и количество ошибок красным цветом, как во время моделирования так и в режиме пост-моделирования (рисунок 21-18).
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| − | {| align=center
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| − | ! [[Файл:Vsim Assertion fail red.gif]]
| + | |
| − | |-
| + | |
| − | ! Figure 21-18. Assertion Failures Appear in Red
| + | |
| − | |}
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| − | <!-- You can use the assertion count command to return the sum of the assertion failure counts for a specified set of assertion directive instances. This command returns a "No matches" warning if the given path does not contain any assertions.
| + | |
| − | -->
| + | |
| − | Вы можете использовать команду <code>[[assertion count]]</code>, чтобы вернуть сумму числа ошибочных утверждений для заданного набора экземляров директив утверждений. Эта команда возвращает предупреждение (warning) "No matches", если заданный путь не содержит никаких утверждений.
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| − | ==== Assertions Window Display Options ====
| + | |
| − | | + | |
| − | <!-- The Assertions window can display assertion directives in hierarchical (tree) mode (Figure 21-19) or in the flattened form (Figure 21-17).-->
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| − | Окно Утверждения могут отображать директивы утверждений в иерархическом (дерево) виде (рисунок 21-19) или в плоском (flattened) виде (рисунок 21-17).
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| − | {| align=center
| + | |
| − | ! [[Файл:Vsim Assertions hierarchy.gif]]
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| − | |-
| + | |
| − | ! Figure 21-19. Hierarchy Display Mode
| + | |
| − | |}
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| − | | + | |
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| − | <!-- The hierarchical display mode can be enabled or disabled by doing any one of the following:-->
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| − | Режим иерархического отображения может быть включен или отключен с помощью одного из следующий действий:
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| − | <!-- * When the Assertions window is docked, select Assertions > Display Options > Hierarchy Mode from the Main menus.-->
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| − | * Когда окно Утверждения пристыкован (docked), выберите ''Assertions → Display Options → Hierarchy Mode'' в главном меню.
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| − | | + | |
| − | <!-- * Right-click in the Assertions window and select Display Options > Hierarchy Mode from the popup menu.-->
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| − | * Щелкните правой кнопкой мыши в окне Утверждения и выберите ''Display Options → Hierarchy Mode'' в всплывающем меню.
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| − | | + | |
| − | <!-- The Display Options menu also includes the following options:-->
| + | |
| − | Меню '''Display Options''' также включает в себя следующие опции:
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| − | <!-- * The Recursive Mode option displays all assertions at and below the selected hierarchy instance, the selection being taken from a Structure window. (i.e., the sim tab). Otherwise only items actually in that particular scope are shown.-->
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| − | * Опция '''Recursive Mode''' отображает все утверждения на выбранном элементе иерархии и ниже, выделение (выбор элемента) берётся из окна Structure (например, закладка sim). В противном случае только показываются только те элементы, которые расположены на выбранному уровне.
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| − | <!-- * The Show All Contexts option displays all instances in the design. It does not following the current context selection in a structure pane. The Show All Context display mode implies the recursive display mode as well, so the Recursive Mode selection is automatically grayed out.-->
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| − | * Опция '''Show All Contexts''' отображает все экземпляры в дизайне. В этом случае не учитывается, что выбрано в текущем контексте в панели Structure. Режим отображения Show All Context означает рекурсивный режим отображения как есть, так что выбор '''Recursive Mode''' автоматически серым цветом. {{Карандаш|24px}}
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| − | | + | |
| − | <!-- * The Show Concurrent Asserts option displays only concurrent assertions.-->
| + | |
| − | * Параметр '''Show Concurrent Asserts''' отображает только параллельные утверждения (concurrent assertions).
| + | |
| − | <!-- * The Show Immediate Asserts option displays only immediate assertions.-->
| + | |
| − | * Параметр '''Show Immediate Asserts''' отображает только непосредственные утверждения (immediate assertions).
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| − | | + | |
| − | === Viewing Cover Directives in the Cover Directives Window ===
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| − | | + | |
| − | The Cover Directives window displays information about cover directives. To open the Cover Directives window, select View > Coverage > Cover Directives.
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| − | | + | |
| − | Figure 21-20 shows PSL cover directives in the Cover Directives window. PSL cover directives are indicated by a purple chevron. SystemVerilog cover directives (not shown) are indicated by a light blue chevron.
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| − | {| align=center
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| − | ! [[Файл:Vsim Cover directives tab.gif]]
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| − | |-
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| − | ! Figure 21-20. PSL Cover Directives in the Cover Directives Window
| + | |
| − | |}
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| − | The Cover Directives window displays accumulated cover directive statistics at the current simulation time, including percentages and a graph for each directive and instance. The plus sign (’+’) to the left of the Name field lets you expand the directive hierarchy to show its elements (properties, sequences, clocks, and HDL signals). Refer to GUI Elements of the Cover Directives Window for a description of each column.
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| − | Display Options for Cover Directives
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| − | Display options allow you to display cover directives in a Recursive Mode or in a Show All Contexts mode. For details, see Changing the Cover Directives Window Display Options.
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| − | Filtering Data in the Assertions and Cover Directives Window
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| − | | + | |
| − | You can filter the Assertions and Cover Directives data displayed by selecting Assertions > Filter > Setup or Cover Directives > Filter > Setup, depending on which window is active. For details, see “Filtering Functional Coverage Data”.
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| − | ===Viewing Memory Profile Data===
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| − | The assertion profile command generates a fine grained profile of memory usage for assertions and cover directives. The results are displayed in the Memory, Peak Memory, Peak Memory Time, and Cumulative Threads columns of the Assertions and Cover Directives windows.
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| − | * The Memory column tracks the current memory used by the assertion or cover directive.
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| − | * The Peak Memory column tracks the peak memory used by the assertion or cover directive.
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| − | * The Peak Memory Time column indicates the simulation run time at which the peak memory usage occurred.
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| − | * The Cumulative Threads column counts the cumulative thread count for the assertion.
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| − | While the Cumulative Threads count is not specifically about memory, it is designed to highlight those assertions and cover directives that are starting too many attempts, such as the following assertion:
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| − | assert property ((@posedge clk) a |=> b);
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| − | If ‘a’ is true throughout the simulation, then the above assertion will start a brand new attempt at every clock. An attempt, once started, will only be alive until the next clock. So this assertion will not appear abnormally high in the Memory and Peak Memory columns, but it will have a high count in the Cumulative Threads column.
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| − | === Viewing Assertions and Cover Directives in the Wave Window ===
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| − | You can view assertions and cover directives in the Wave window just like any other signal in your design. Use one of the following methods to add directives to the Wave window:
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| − | * To add all assertions in your design to the Wave window,
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| − | ** Select a single object in the Assertions window, then select Add > To Wave > Objects in Design from the main menus.
| + | |
| − | ** Select all objects in the Assertions window, then select Add > To Wave > Selected Objects from the main menus
| + | |
| − | ** Right-click the selected assertions, then select Add Wave > Objects in Design from the popup menu.
| + | |
| − | ** Select all objects in the window, then click the Add Selected To Window button in the Standard Toolbar.
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| − | * To add all cover directives in your design to the Wave window:
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| − | ** Select a single directive in the Cover Directives window, then select Add > To Wave > Functional Coverage in Design from the main menus.
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| − | ** Select all directives in the Cover Directives window, then select Add > To Wave > Selected Functional Coverage from the main menus.
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| − | ** Right-click the selected cover directives, then select Add Wave > Functional Coverage in Design in Design from the popup menu.
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| − | ** Select all directives in the window, then click the Add Selected To Window button in the Standard Toolbar.
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| − | * To place a single assertion or cover directive in the Wave window:
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| − | ** Drag the object from the its window and drop it into the Wave window, or simply drop it onto the Wave tab if it is showing.
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| − | ** Select the object, then click the Add Selected To Window button in the Standard Toolbar.
| + | |
| − | ** Select the object then select Add > To Wave > Selected Objects from the menu bar.
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| − | * Right-click any selected assertion and select Add Wave > Selected Objects from the popup menu; or right-click any selected cover directive and select Add Wave > Selected Functional Coverage from the popup menu.
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| − | Questa SIM represents assertions and cover directives as signals or waveforms in the Wave window. The Wave window in Figure 21-21 shows several SystemVerilog assertions and a single cover directive. SystemVerilog assertions are represented by light blue triangles in the pathnames column. SystemVerilog cover directives are represented by light blue chevrons.
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| − | {| align=center
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| − | ! [[Файл:Vsim Sv assert wave.gif]]
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| − | |-
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| − | ! Figure 21-21. SystemVerilog Assert and Cover Directives in the Wave Window
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| − | |}
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| − | The Wave window in Figure 21-22 shows several PSL assertions and cover directives. PSL assertions are represented by magenta triangles. PSL cover directives are represented by magenta chevrons.
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| − | {| align=center
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| − | ! [[Файл:Vsim Assertions wave.gif]]
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| − | |-
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| − | ! Figure 21-22. PSL Assert and Cover Directives in the Wave Window
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| − | |}
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| − | The name of each assertion and cover directive comes from the assertion code. The plus sign (’+’) to the left of the name indicates that an assertion or cover directive is a composite trace and can be expanded to show its elements (properties, sequences, clocks, and HDL signals). Note that signals are flattened out; hierarchy is not preserved.
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| − | The value in the value pane is determined by the active cursor in the waveform pane. The value will be one of ACTIVE, INACTIVE, PASS, FAIL, or ANTCDENT.
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| − | The waveform for an assertion or cover directive represents both continuous and instantaneous information.
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| − | * Continuous information is either active or inactive. The directive is active anytime it matches the first element in the directive. When active, the trace is green; when inactive it is blue.
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| − | * Instantaneous information is represented as a start, pass, or fail event. A start event is shown as a blue square. A green triangle represents a pass. And a red triangle indicates a fail.
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| − | A yellow triangle represents an antecedent match (Figure 21-23). The yellow triangle is displayed only if the directive is browseable and assertion debug is on (vsim -assertdebug). The yellow triangle is shown for each thread of the assertion under ActiveCount in the assertion (see Using the Assertion Active Thread Monitor). The signal values of the assertion also reflect the antecedent match (ANTCDENT).
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| − | {| align=center
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| − | ! [[Файл:Vsim Wave antecedent.gif]]
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| − | |-
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| − | ! Figure 21-23. Antecedent Matches Indicated by Yellow Triangle
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| − | |}
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| − | Table 21-1 summarizes the graphic elements for assertions and cover directives used in the Wave and ATV windows (see Viewing Assertion Threads in the ATV Window):
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| − | {| class=standard align=center
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| − | |+ Table 21-1. Graphic Elements for Assertions and Cover Directives
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| − | ! Graphic element
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| − | ! Meaning
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| − | |-
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| − | | blue line
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| − | |assertion or cover directive is inactive
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| − | |-
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| − | |green line
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| − | |assertion or cover directive is active
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| − | |-
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| − | |blue square
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| − | |assertion or cover directive starts
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| − | |-
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| − | |green triangle
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| − | |assertion or cover directive passed
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| − | |-
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| − | |red triangle
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| − | |assertion or cover directive failed
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| − | |-
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| − | |yellow triangle
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| − | |antecedent match occurred in assertion
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| − | |}
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| − | ==== Displaying Cover Directives in Count Mode ====
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| − | You can change the coverage directive waveform in the Wave window so it displays in count mode format, which shows the instantaneous waveform value as a decimal integer. To change to count-mode format, right-click a coverage waveform name and select Cover Directive View > Count Mode.
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| − | {| align=center
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| − | ! [[Файл:Vsim Sv count mode.gif]]
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| − | |-
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| − | ! Figure 21-24. Viewing Cover Directive Waveforms in Count Mode
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| − | |}
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| − | Count mode can be useful for gauging the effectiveness of stimulus over time. If all cover directive counts are static for a long period of time, it may be that the stimulus is acting in a wasteful manner and can be improved.
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| − | === Comparing Assertions ===
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| − | Questa SIM’s compare feature allows you to compare assertions (which includes any assertion-like object such as accAssertion, accCover, accEndpoint, or accImmediateAssert.) There is no cross-compare with assertion types outside the set listed, and assertion compare is further limited to like types only. That is, both the reference and test items must be of the same type.
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| − | Comparing assertion signals differs from comparing normal HDL signals/ports because assertion signals have two attributes:
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| − | The current assertion state (ACTIVE | INACTIVE)
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| − | The current assertion event (START | PASS | FAIL | EVAL)
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| − | Assertions expand to show child signals but these child signals don't participate in the compare evaluation. Child signals are, however, visible in the compare waveforms when the you expand compare assertions.
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| − | Setting Up the Assertions Compare
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| − | You can set up and run an assertion compare using the compare commands or the menu-based Waveform Comparison Wizard. For example, a comparison using compare commands may look like the following:
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| − | | + | |
| − | add wave /top/assert_sig
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| − | run 1000 ns
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| − | dataset open vwim_test.wlf
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| − | compare start sim vsim_test
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| − | compare add sim:/top/assert_sig vsim_test:/top/assert_sig
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| − | compare run
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| − | All existing compare commands are supported for comparing assertion signals. Refer to the Command Reference for syntax and command descriptions.
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| − | The Waveform Comparison Wizard will guide you through the selection of a reference dataset and a test dataset. Assertions within those datasets are compared along with other signals. You can start the Wizard is by selecting Tools > Waveform Compare > Comparison Wizard.
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| − | The Compare Signal
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| − | When two assertion signals are compared — for example, vsim_pass:/top/my_assertion_sig and vsim_fail:/top/my_assertion_sig — a third virtual signal is created:
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| − | | + | |
| − | compare:/top/\my_assertion_sig<>my_assertion_sig\
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| − | The compare signal created is composed of the reference signal and the test signal. Differences between the reference and text assertion signals are highlighted in red in the compare signal when it is displayed in the Wave Window. Assertion differences cannot be viewed in the ATV window.
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| − | Two Types of Assertion Differences
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| − | There are two types of assertion differences:
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| − | Instantaneous difference — When the assertion event (START | PASS | FAIL | EVAL) is different but the state of the assertion (ACTIVE | INACTIVE) is the same.
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| − | For example, considering two datasets vsim_top and vsim_ntop with an assertion signal my_assertion_sig.
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| − | vsim_top:/top/my_assertion_sig is PASS_INACTIVE at 20 ns
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| − | vsim_ntop:/top/my_assertion_sig is FAIL_INACTIVE at 20ns
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| − | This is an instantaneous difference the difference will marked at time 20 ns and the width of the difference marker will be equal to the width of the PASS/FAIL symbol.
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| − | Range difference — When there is a state change (ACTIVE->INACTIVE) or vice-versa, between the reference and test assertion, irrespective of the event on the assertions.
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| − | Child Signals
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| − | An assertion object is composed of child signals. It is the evaluation of these child signals that determine the assertion event (START/PASS/FAIL). If you choose to expand the assertion, the difference marker is propagated to the child signals as well, but this may not necessarily mean a change in value on the child signal at that specific time — the difference could have occurred earlier.
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| − | If the reference signal has child signals but the test signal does not, or vice-versa, waveform compare will still work because compare cares only about the absolute event on the assertion. If there is a difference, it will be marked.
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| − | [[Категория:PSL]]
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