OVM/Книги — различия между версиями
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Версия 22:19, 16 марта 2013
- Glasser M. Open Verification Methodology Cookbook — USA: Springer, 2009. — 248 с. — ISBN 978-1-4419-0967-1.
- Хаханов В.И., Хаханова И.В., Литвинова Е.И., Гузь О.А. Проектирование и верификация цифровых систем на кристаллах. Verilog & Symtem Verilog — Харьков: ХНУРЭ, 2010. — 528 с.
- Srikanth Vijayaraghavan, Meyyappan Ramanathan A Practical Guide for SystemVerilog Assertions — Springer, 2005. — 334 с.
- Mike Mintz, Robert Ekendahl Hardware Verification With SystemVerilog: An Object-oriented Framework — Springer, 2007. — 332 с.
- Mike Mintz, Robert Ekendahl Hardware Verification With SystemVerilog: An Object-oriented Framework — Springer, 2007. — 299 с.
- Sponsor, Design Automation Standards Committee of the IEEE Computer Society and the IEEE Standards Association Corporate Advisory Group IEEE standard 1800-2009 for SystemVerilog--unified hardware design, specification, and verification language — Springer. — 1285 с.
- Sasan Iman Step-by-step Functional Verification with SystemVerilog and OVM — Hansen Brown Publishing, 2008. — 520 с.
- Stuart Sutherland, Simon Davidmann, Peter Flake, P. Moorby SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling — Springer, 2006. — 436 с.
- Stuart Sutherland SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling — Springer, 2006. — 435 с.
- Chris Spear SystemVerilog for Verification, Second Edition: A Guide to Learning the Testbench Language Features — Springer, 2008. — 455 с.
- Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny The Power of Assertions in SystemVerilog — Springer, 2010. — 562 с.
- Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale Verification Methodology Manual for SystemVerilog Bergeron Cerny Hunter Nightingale — Springer, 2005. — 528 с.
- Stuart Sutherland, Don Mills Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them — Springer, 2007. — 230 с.
- Janick Bergeron Writing Testbenches using SystemVerilog — 2006. — 440 с.
