PSL/A Practical Introduction to PSL/SERE Style

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PSL

• The Designer's Guide To PSL (ru)

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Литература

• Литература
• IEEE Std 1850-2010
• Embedded PSL in VHDL (en)

Введение в PSL

• 1. Introduction (en)
• 2. Basic Temporal Properties (en)
• 3. Some Philosophy (en)
• 4. Weak vs. Strong Temporal Operators (en)
• 5. SERE Style (en)

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• Словарь терминов
• Дневник
• История проекта

* VHDL * OS-VVM * Co-Simulation *

(i) SERE 5.1a matches both 1 and 2. SERE 5.1b matches 1, but not 2.
{(req out && !ack) ; (busy && !ack)[*] ; ack} (5.1a) {(req out && !ack) ; (busy && !ack)[*] ; ack && !busy} (5.1b)
Fig. 5.1: Two simple SEREs